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2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
Crystal Oscillator
The crystal oscillator has been optimized to work with
low-cost crystals (e.g., Kyocera CX-3225SB). See Figure
1. The crystal oscillator frequency can be fine tuned
through bits D6:D0 in Register 14 (A3:A0 = 1110), which
control the value of C TUNE from 0.5pF to 15.4pF in
0.12pF steps. See the Crystal-Oscillator Offset
Frequency vs. Crystal-Oscillator Tuning Bits graph in the
Typical Operating Characteristics . The crystal oscillator
can be used as a buffer for an external reference fre-
quency source. In this case, the reference signal is AC-
coupled to the XTAL pin, and capacitors C1 and C2 are
not connected. When used as a buffer, the XTAL input
pin has to be AC-coupled. The XTAL pin has an input
impedance of 5k ? || 4pF, (set D6:D0 = 0000000 in
Register 14 A3:A0 = 1110).
MAX2831
MAX2832
Reference Clock Output Divider/Buffer
The reference oscillator of the MAX2831/MAX2832 has
a divider and a buffered output for routing the refer-
ence clock to the accompanying baseband IC. Bit D10
in Register 14 (A3:A0 = 1110) sets the buffer divider to
divide by 1 or 2, independent of the divide ratio for the
reference frequency provided to the PLL. Bit B9 in the
same register enables or disables the reference buffer
output. See the Clock Output waveform in the Typical
Operating Characteristics .
Loop Filter
The PLL charge-pump output, CPOUT (pin 24), con-
nects to an external third-order, lowpass RC loop-filter,
which in turn connects to the voltage tuning input,
TUNE (pin 32), of the VCO, completing the PLL loop.
The charge-pump output sink and source current is
1mA, and the VCO tuning gain is 103MHz/V at 0.5V
tune voltage and 86MHz/V at 2.2V tune voltage. The RC
loop-filter values have been optimized for a loop band-
width of 150kHz, to achieve the desired Tx/Rx turn-
around settling time, while maintaining loop stability
XTAL
C1
CTUNE
28
29
and good phase noise. Refer to the MAX2831 EV kit
schematic for the recommended loop-filter component
values. Keep the line from this pinto the tune input as
short as possible to prevent spurious pickup.
C2
C TUNE
1.35k ?
5.9k ?
Lock-Detector Output
The PLL features a logic lock-detect output. A logic-high
indicates the PLL is locked, and a logic-low indicates
the PLL is not locked. Bit D5 in Register 5 (A3:A0 =
0101) enables or disables the lock-detect output. Bit
FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN
Figure 1. Crystal Oscillator Schematic
D12 in Register 1 (A3:A0 = 0001) configures the lock-
detect output as a CMOS or open-drain output. In open-
drain output mode, bit D9 in Register 5 (A3:A0 = 0101)
enables or disables an internal 30k ? pullup resistor
from the open-drain output.
26
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